1. Technical Field
The present invention relates to a semiconductor device, and to a method of manufacturing the same.
2. Related Art
The ongoing reduction in spacing width between interconnects in semiconductor devices has originated various issues that lead to degradation in reliability of the semiconductor devices. One of such issues is Time Dependent Dielectric Breakdown (hereinafter, TDDB). The TDDB resistance between the interconnects is degraded as the spacing between the interconnects becomes narrower. In other words, the narrower the spacing between the interconnects is, the less resistant the resist employed in the formation of the interconnects becomes against the etching process. This makes the formation process more difficult, leading to an increase in line edge roughness (LER) of the interconnects, which often provokes the TDDB.
The TDDB resistance can be enhanced by an ammonia plasma process, i.e. irradiating a semiconductor substrate having the interconnects exposed on its surface with an ammonia plasma. In this process, however, a stress induced void (hereinafter, SIV) is prone to take place when the semiconductor device includes copper interconnects. The SIV is another factor that leads to the degradation in reliability of the semiconductor devices.
To cope with such problems, Japanese Laid-open patent publications No. H10-189604, No. H11-204523 and No. 2004-193544 propose performing the ammonia plasma process on a semiconductor substrate having a copper interconnect exposed on its surface, after a silane process of exposing the semiconductor substrate in silane atmosphere. A method of performing the both before and after the silane process is disclosed in the documents: Laurent G. Gosset et al., “Integration and characterization of a self-aligned barrier to Cu diffusion based on copper silicide”, 2003 Advanced Metallization Conference Proceedings, USA, Materials Research Society, Oct. 21, 2003, p. 321-328; and L. G. Gosset et al., “Integration and performances of an alternative approach using copper silicide as a self-aligned barrier for 45 nm technology node Cu interconnects”, 2004 International Interconnect Technology Conference Proceedings, USA, IEEE, June 2004. In addition, U.S. Pat. No. 6,599,827 proposes executing the ammonia plasma process only before the silane process.